1. Field of the Invention
The present invention relates to a synchronization compensating circuit for use in a scanning type display circuit, and more specifically, a circuit for compensating a synchronization deviation in a synchronization circuit which generates on the basis of a basic clock a scanning clock used in a circuit for superimposing characters or figures into a scan type display screen of a television receiver, a video display, etc.
2. Description of Related Art
In the prior art, one typical conventional synchronization circuit includes a multistage delay circuit connected to receive a basic clock, which is composed of a system clock used for driving an overall system, or a clock obtained by dividing or multiplying the basic clock. For example, the multistage delay circuit includes K delay stages connected in series, and each of the K delay stages gives a delay of T/(K+1) where T is a period of the basic clock applied to the multistage delay circuit. Thus, the multistage delay circuit outputs K delayed clocks which are delayed by T/(K+1), 2T/(K+1), . . . , KT/(K+1), respectively. The synchronization circuit also includes a timing generator receiving a horizontal synchronization signal and operating to cause to select among the delayed clocks one delayed clock which becomes a high level within a constant time after receipt of each horizontal synchronization signal. Thereafter, the delayed clock having the same delay time as that of the selected delayed clock is outputted in each period of the basic clock as a scanning clock until a next horizontal synchronization signal is applied. In the above mentioned manner, a deviation of the obtained scanning clock from the horizontal synchronization signal has only the delay time of one stage of the multistage delay circuit at maximum.
However, the delay stages of the multistage delay circuit do not necessarily have a constant predetermined or designed delay time because of variation in manufacturing process, but rather, have a relatively large variation in delayed time. In addition, the designed delay time of each delay stage of the multistage delay circuit is often shortened or elongated upon variation in temperature. If the delay time of each delay stage of the multistage delay circuit is shortened, there will occur the case that the horizontal synchronization clock is applied after a rising edge of the maximum delayed clock before a rising edge of a next basic clock, and as a result, no scanning clock is generated. On the other hand, if the delay time of each delay stage of the multistage delay circuit is elongated, there will occur the case that two (or more) delayed clocks are outputted as the scanning clock in the same period of the basic clock.